1. Field of the Invention
The present invention relates to a thin-film transistor (TFT) and to a method of manufacturing the same. Particularly, the present invention relates to a method of manufacturing a bottom gate-type thin-film transistor in which the gate electrode is disposed on the side of the substrate rather than the side of the semiconductor layer.
2. Description of Related Art
In active matrix-type liquid crystal displays (LCDS) or organic electroluminescence (EL) displays, a substrate is generally used in which drive circuits and TFTs for selecting a pixel are formed on a transparent insulating substrate made of material such as glass. In order to form semiconductor elements on the transparent substrate, it is impossible to implement a high temperature process and to diffuse impurities into the transparent substrate. This differs from the case where the silicon substrate is used. Hence, when semiconductor elements are formed on a glass substrate, an approach different from the method of forming semiconductor elements on a silicon substrate must be employed.
One conventional method of forming bottom gate-type TFTs on a glass substrate will be described below. Referring to FIGS. 1A to 1E, a P-channel TFT is depicted on the right side while an N-channel TFT is depicted on the left side.
Step 1; As shown in FIG. 1A, a conductive film of a refractory (high-melting point) metal such as chromium is formed on the glass substrate 51. The conductive film is etched in a predetermined pattern to form a gate electrode 52. Next, a gate insulating film 53, which is a laminated structure of a silicon dioxide and a silicon nitride, is formed covering the gate electrodes 52, and then a semiconductor layer 54 of a silicon, and an ion stopper 55 of a silicon dioxide are sequentially formed.
Step 2: As shown in FIG. 1B, a photoresist film is coated over the entire intermediate structure. Light is illuminated onto the photoresist film from the side of the substrate 51. Using the gate electrode 52 as a mask, the photoresist film is exposed to light and developed to form a resist mask 56. N-type impurities are implanted or doped at a low concentration into the semiconductor layer 54 while the resist mask 56 and the ion stopper 55 are used as a mask. Thus, an Nxe2x88x92 region is formed. Since the resist mask 56 is formed, with the gate electrode 52 acting as a mask, the Nxe2x88x92 region is self-aligned with the gate electrode 52.
Step 3: As shown in FIG. 1C, a resist mask 57 is formed to completely cover the P-channel TFT and is slightly larger than the gate electrode 52 of the N-channel TFT. N-type impurities are heavily implanted into the semiconductor layer 54 to form an N+ region. Thus, an LDD (lightly Doped Drain) structure can be obtained.
Step 4: As shown in FIG. 1D, the resist mask 57 is removed. A resist mask 58 is newly formed to cover the N-channel TFT. Next, P-type impurities are doped into the semiconductor layer 54, with the ion stopper 55 acting as a mask, to form a P+ region. Because the ion stopper 55 is formed to act as a mask for the gate electrode 52, the P+ region is aligned with the gate electrode 52.
Step 5: As shown in FIG. 1E, an interlayer insulating film 59 formed of a laminated structure of silicon dioxide and silicon nitride is formed all over the intermediate structure. At this point, because the interlayer insulating film 59 is integrated with the ion stopper 55, the boundary becomes unclear. Next, contact holes are opened in the interlayer insulating film 59 at predetermined positions. Thereafter, the source electrodes 60 and the drain electrodes 60 are formed to complete the TFTs.
As described above, in Step 4, the P-type impurities are doped while the ion stopper 55 is used as a mask. At the same time, the P-type impurities are doped into the semiconductor layer 54 and the stopper 55.
However, there is variation in the operational characteristics of bottom gate-type thin-film transistor produced through the above-described process. It is considered that variations in the TFT characteristics are caused by an occurrence of back channel. It has also been considered that such back channel results from other wire layer or electrodes disposed above the semiconductor layer 54 via the thick insulating layer formed of at least the ion stopper 55 and the interlayer insulating film 59. However, the characteristics of the bottom gate-type thin-film transistor vary over the expected effect of a back channel caused by such the conductive layer. Reduction in variation of characteristics resulting from the back channel, regardless of root cause, has long been desired in the field.
An object of the present invention is to provide a method of manufacturing a bottom gate-type thin film transistor in which variations in characteristics can be reduced.
Another object of the present invention is to provide a bottom gate-type thin film transistor produced by the above-described method.
The present invention is made to solve the above-described problems. According to the present invention a bottom gate-type thin-film transistor comprises a gate electrode formed on a transparent insulating substrate; a gate insulating film overlying the gate electrode; and a semiconductor layer formed on the gate insulating film, the semiconductor layer having source and drain regions doped with impurities, and a channel region; an interlayer insulating film is formed on the semiconductor layer; and in said interlayer insulating film, a region in a vicinity of at least an interface between at least the channel region in the semiconductor layer and the interlayer insulating film has an impurity concentration of 1018 atom/cc or less.
The present applicant has studied variations in characteristic of a bottom gate-type thin-film transistor produced according to conventional methods. As a result, the present inventors found out that impurities in the interlayer insulating film 59 covering the channel region of the TFT induce back channel, thus influencing the characteristic variations. Conventionally, for example, as shown in FIG. 1D, P-type impurities are doped into the semiconductor layer 54 to form a P-channel TFT while the ion stopper 55 acts as a mask. The impurity concentration is set to a sufficiently heavy value to form the source region and the drain region in the semiconductor layer 54. P-type impurities such as boron or N-type impurities such as phosphorus and arsenic are heavily doped into even the ion stopper 55. The impurities are heavily doped into the interlayer insulating film 59 and reside therein. The remaining impurities cause variations in the gate threshold of the TFT.
According to the present invention, a region of said interlayer insulating film at least in the vicinity of the interface between the interlayer insulating film and the channel region of the semiconductor layer, the doping concentration of impurities for activating the semiconductor layer is set to 1018 atoms/cc or less. Because this configuration suppresses the occurrence of back channel resulting from the impurities contained in the interlayer insulating film, variations in the TFT characteristics can be decreased.
In another aspect of the present invention, a bottom gate-type thin-film transistor comprises a gate electrode formed on a transparent insulating substrate; a gate insulating film overlying the gate electrode; a semiconductor layer formed on the gate insulating film, the semiconductor layer having a source and a drain region, impurities being doped, and a channel region; and an interlayer insulating film formed on the semiconductor layer, wherein both the interlayer insulating film and the semiconductor layer are in direct contact each other and are disposed above the gate electrode.
As described above, in the bottom gate-type thin-film transistor according to the present invention, the interlayer insulating film is in direct contact with the semiconductor layer; the ion stopper does not intervene. This structure can prevent the back channel phenomenon caused by impurities contained in the interlayer insulating film. Therefore, manufacturing variations among bottom gate-type thin-film transistors can be reduced.
According to another aspect of the invention, a method for manufacturing a bottom gate-type thin-film transistor on a transparent insulating substrate comprises the steps of forming a gate electrode on a transparent substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming a mask on the semiconductor layer corresponding to the gate electrode; doping impurities selectively into the semiconductor layer, using the mask; and forming an interlayer insulating film on the semiconductor layer, after removal of the mask.
According to the present invention, a bottom gate-type thin-film, which has characteristics identical to that of the prior art, can be easily produced without forming the problematic stopper insulating film which leads to decreases in characteristic.
Moreover, before formation of the mask, a native oxide film may be formed on the semiconductor layer. After removal of the mask, residue of the mask may be removed together with the native oxide film.
Moreover, a dilute hydrofluoric acid may be used to remove the native oxide film.
As described above, the resist mask can be removed together with the native oxide film such that it will not remain between the semiconductor layer and the interlayer insulating film. As a result, a bottom gate-type thin-film transistor with excellent characteristics can be produced.